Previous simulation models of complex VLSI integrated circuits either have been implemented solely in software (and thus have suffered from significant cost and performance limitations) or have required an actual physical specimen of the VLSI device being simulated (thereby limiting the feasibility of using such a model for debugging the VLSI device prior to fabrication).
When U.S. Pat. No. 4,590,581, entitled "Method and Apparatus For Modeling Systems of Complex Circuits" (the "Widdoes Patent") was filed on May 9, 1983, it was certainly the case that pure software models of complex logic devices were simply too slow to permit real-time simulation of a digital computer system. It is thus not surprising that the Widdoes Patent addressed this problem by providing a method for modeling the operation of a complex VLSI device in hardware, using an actual physical specimen of the VLSI device being modeled and a "personality module" which enabled that device to communicate in "real time" with a software simulation model of the other components in a digital computer system.
Currently, however, computer aided design tools permit the simulation in software of complex VLSI devices at speeds exceeding 10 MIPS ("million instructions per second"). Moreover, it has been estimated that the performance of such simulations will increase dramatically in the next decade, with systems attaining speeds in the "thousands of MIPS."
Such performance levels might at first blush appear to make pure software simulation models once again a viable alternative. Yet, as also noted in the Widdoes Patent, software simulation models have additional disadvantages. They are generally costly and time consuming to develop, particularly for a board manufacturer endeavoring to model the operation of a digital computer system comprising complex VLSI devices which are manufactured by others and are provided with extremely limited detailed specifications.
The solution provided by the Widdoes Patent enabled the simulation of a digital computer system in which an actual physical specimen of one complex VLSI device (such as the Motorola 68000 microprocessor) was coupled with various other devices simulated in software. As mentioned above, a personality module (i.e., a gate array device external to the VLSI device) enabled the slower simulation model to interact with the VLSI device which executed in real time.
In essence, the Widdoes Patent was directed at the problem of debugging various hardware devices of a digital computer system in a real-time environment. Although most of the hardware devices in such a system were capable of being modeled in software (enabling significantly greater debugging capabilities, including conditional assembly, the setting of breakpoints and the examination of internal states), it was simply not feasible to develop a software model for certain complex VLSI devices, particularly state of the art microprocessors such as the Motorola 68000. System designers incorporating such complex VLSI devices thus benefitted from the invention disclosed in the Widdoes Patent, which facilitated the effective debugging of the other hardware devices in their computer system in a real time system environment.
Although the invention disclosed in the Widdoes Patent facilitates the effective debugging of these other hardware devices, it suffers from a number of significant disadvantages when applied generally to today's problem of modeling digital computer systems in a real-time environment.
To begin with, it appears from the disclosure in the Widdoes Patent that only one complex device can be incorporated into the system, because all other devices must be simulated in software. Moreover, even if physical specimens of multiple VLSI devices could be incorporated, a customized personality module would have to be developed for each such device, a complex and costly solution likely to yield many errors. Finally, locating personality modules on the system board itself presents additional timing and other problems with respect to the integration of a "foreign" device (the personality module) into the actual computer system being tested.
As mentioned above, the advances in the performance of software simulation tools now permit effective software modeling, even of relatively complex ASIC devices, by the company who manufactures such devices pursuant to individual customers' specifications. The problem results, however, from the fact that an ASIC device, though it may have executed the test vectors provided by the customer with a 100% success rate (both in simulation and in physical device operation), will nevertheless often yield a much lower success rate when the actual ASIC chip is fabricated, plugged into a board and tested with the entire system.
In short, current chip-level simulation models have insufficient test vectors for the ASIC chip in a systems environment. What is needed is a real-time, systems-level simulation model of the computer system in which the customer's ASIC device will be incorporated. Such a systems model running in real time will generally expose the physical ASIC device to more complete test vectors than were provided initially to the software model of the ASIC device. See "The Era of the Microprocessor," Electronic Engineering Times Anniversary Issue, November, 1987, for a general discussion of this problem.
Whereas the Widdoes Patent addresses the simulation of certain hardware devices in a digital computer system, other simulation models have been aimed at the development and debugging of software executed by particular hardware devices in the system (such as general purpose microprocessors).
In-circuit emulators, such as those developed by Intel, as well as other hardware emulators, facilitate the development and debugging of software by providing a "black box" (the emulator) which is coupled to an actual physical specimen of the hardware device being emulated (e.g., the microprocessor which will execute the software being developed). The hardware emulator enables the software developer to interrupt execution of his/her software and examine certain internal states (generally by means of a personal computer also coupled to the emulator) far more easily than would otherwise be possible with mere software debugging tools.
Neither these hardware emulators nor the simulation model disclosed in the Widdoes Patent, however, provide a feasible solution to what is perhaps the most significant problem facing today's ASIC developers: the simulation of an ASIC device in a real-time systems environment prior to fabrication.
Practicality demands that the ASIC device be simulated and debugged (preferably in a real-time system environment) before it is fabricated. The invention disclosed in the Widdoes Patent does not address this problem. Although current simulation tools enable the creation of a software model for the ASIC device being developed for a particular customer, the approach adopted in the Widdoes Patent would require that either a separate software simulation model or a customized gate array (personality module) be developed for each of the other devices in the customer's system. This is clearly not practical.
Moreover, hardware emulators also require an actual physical specimen of the device being emulated. This approach is feasible when the purpose is not to debug that device, but to debug software being developed for execution on that device (or to verify a device that has been fabricated, checking if it operates with the test vectors as did the software model). When the purpose is to debug an ASIC device in a real-time systems environment, however, the cost of fabricating that device each time it is to be simulated is prohibitive.
Rarely can every device in the customer's desired computer system be modeled in software. The time and expense required by such an approach are simply too great to be feasible. Thus, a simulation model is required which enables the ASIC device under development to be modeled in software, but which permits that device to be simulated in real time in the actual computer system (comprising either physical specimens or software models of the other devices in the system) in which the ASIC device will be incorporated. Such a model is explained below.